Microelectronics devices are being developed with substrates of increasingly larger areas, yet there remains strong incentives to package these devices in conventional molded plastic packages. As the substrate area increases relative to the package, it becomes increasingly difficult to properly fill the mold. A large area substrate essentially divides the mold cavity into separate cavities above and below the substrate. The ability for molding compound to flow uniformly on both sides of the substrate diminishes with increased substrate area due to the reduced flow "communication" around the edges of the substrate. Any lead and lag of the flow fronts on either side of the substrate is no longer compensated by flow around the edges of the substrate.
Electronic devices with large area substrates include board mounted power modules (BMPMs) with large printed wiring board (PWB) substrates; thin, small outline packages (TSOPs) with large silicon die; multi-chip modules (MCMs) with silicon, ceramic or laminate substrates; and hybrid integrated circuits (HICs) with large ceramic or laminate substrates. These devices have substrate area to package area ratios (S/P ratios) ranging from 0.59 to 0.87 (see Table 1); whereas S/P ratios for conventional silicon device packages are typically 0.10 to 0.35.
TABLE 1 ______________________________________ Typical substrate area to package area ratios for various electronic components. BMPMs TSOPs MCMs HICs ______________________________________ substrate 1.08 .times. 1.9 0.425 .times. 0.335 0.9 .times. 0.9 1.0 .times. 1.0 dimensions (in) package 1.18 .times. 2.0 0.49 .times. 0.395 1.17 .times. 1.17 1.14 .times. 1.14 dimensions (in) S/P ratio 0.87 0.74 0.59 0.76 ______________________________________